Conductive pattern and display device having the same

ABSTRACT

A conductive pattern includes an organic insulating layer, a first conductive layer provided on the insulating layer and including at least a first sub-conductive layer, and an additional conductive layer provided between the insulating layer and the first conductive layer, or on the first conductive layer, wherein the additional conductive layer includes a metal nitride.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to, and the benefit of, Korean PatentApplication No. 10-2016-0183376 filed on Dec. 30, 2016 in the KoreanIntellectual Property Office, the entire contents of which areincorporated herein by reference in their entirety.

BACKGROUND 1. Field

Embodiments of the inventive concept relate to a conductive pattern anda display device having the same.

2. Description of the Related Art

A display device may include a plurality of pixels including displayelements. Wring lines and at least one transistor connected to thewiring lines and configured to drive the display device may be arrangedin each of the pixels. The transistor may be electrically connected tothe display device and drive the display element by using signalsapplied from the wring lines.

At least a portion of the wiring lines may be disposed on an organiclayer and lower portions of the wiring lines may directly contact theorganic layer. When the wiring lines directly contact the organic layer,the wiring lines and the organic layer may react with each other duringthe formation of the wiring lines, so that an oxide of a materialincluded in the wiring lines or a composite material including materialsincluded in the organic layer and the wiring lines may be formed at theinterface between the wiring lines and the organic layer.

The oxide or the composite material may not be removed at the same timeas the material included in the wiring lines when the wiring lines arepatterned.

SUMMARY

Embodiments of the inventive concept provide a conductive patternpreventing a reaction with an organic layer.

Embodiments of the inventive concept also provide a display deviceincluding the conductive pattern.

According to some exemplary embodiments of the present inventiveconcept, a conductive pattern may include an insulating layer includingorganic material, a first conductive layer provided on the insulatinglayer and including at least a first sub-conductive layer, and anadditional conductive layer provided between the insulating layer andthe first conductive layer, or on the first conductive layer, whereinthe additional conductive layer includes a metal nitride.

The additional conductive layer may be a second conductive layerprovided between the insulating layer and the first conductive layer.

The first conductive layer may further include a second sub-conductivelayer provided between the second conductive layer and the firstsub-conductive layer, and the second conductive layer may include anitride of a material included in the second sub-conductive layer.

The second sub-conductive layer may include titanium (Ti).

The second conductive layer may include a titanium nitride.

The conductive pattern may further include a third sub-conductive layerprovided on the first sub-conductive layer, wherein the thirdsub-conductive layer includes the same material as the secondsub-conductive layer.

The third sub-conductive layer may include titanium (Ti).

The conductive pattern may further include a third conductive layerprovided on the first sub-conductive layer, wherein the third conductivelayer includes the same material as the second conductive layer.

The third conductive layer may include a titanium nitride.

The first sub-conductive layer may include at least one of gold (Au),silver (Ag), copper (Cu), aluminum (Al) and an alloy thereof.

According to some exemplary embodiments of the present inventiveconcept, a display device may include a substrate including a displayarea and a non-display area, at least one transistor provided in thedisplay area of the substrate, a first insulating layer covering thetransistor, a first bridge pattern provided on the first insulatinglayer and connected to the transistor, a second insulating layercovering the first bridge pattern and including an organic insulatingmaterial, a second bridge pattern provided on the second insulatinglayer and connected to the first bridge pattern, and a display elementconnected to the second bridge pattern, wherein the second bridgepattern comprises: a first conductive layer including at least a firstsub-conductive layer, and a second conductive layer provided between thesecond insulating layer and the first conductive layer, wherein thesecond conductive layer includes a metal nitride.

The first insulating layer includes an organic insulating material,wherein the first bridge pattern comprises: a first conductive layerprovided on the first insulating layer and including at least a firstsub-conductive layer, and a second conductive layer provided between thefirst insulating layer and the first conductive layer, wherein thesecond conductive layer includes a metal nitride.

According to some exemplary embodiments of the present inventiveconcept, a display device may include a substrate including a displayarea and a non-display area, at least one transistor provided in thedisplay area of the substrate, a display element connected to thetransistor, and a conductive pattern connected to the transistor or thedisplay element and provided on an organic layer, wherein the conductivepattern comprises: a first conductive layer including at least a firstsub-conductive layer, and a second conductive layer provided between theorganic layer and the first conductive layer, wherein the secondconductive layer includes a metal nitride.

According to some exemplary embodiments of the present inventiveconcept, a conductive pattern may include an insulating layer includingorganic material, a first conductive layer provided on the insulatinglayer and including at least a first sub-conductive layer, and anadditional conductive layer provided between the insulating layer andthe first conductive layer, or on the first conductive layer, whereinthe additional conductive layer includes a material not reacting with amaterial included in the insulating layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a perspective view illustrating a display device according toan embodiment of the present inventive concept.

FIG. 2 is a plan view illustrating a display device shown in FIG. 1.

FIG. 3 is an equivalent circuit diagram illustrating a pixel accordingto an embodiment of the present inventive concept.

FIG. 4 is a detailed plan view illustrating a pixel shown in FIG. 3.

FIG. 5 is a cross-sectional diagram taken along the line II-II′ of FIG.4.

FIG. 6 is a cross-sectional diagram taken along the line III-III′ ofFIG. 4.

FIGS. 7A and 7B are enlarged views of an area EA1 of FIG. 5.

FIG. 8 is an enlarged view of an area EA2 of FIG. 5.

FIGS. 9, 10, 11 and 12 are electron microscopic images showing aconductive pattern formed on an organic layer including polyimide.

FIGS. 13, 14, 15 and 16 are high-angle annular dark-field (HAADF) imagesshowing a conductive pattern formed on an organic layer includingpolyimide.

FIG. 17 is a cross-sectional diagram taken along the line I-I′ of FIG.2.

FIG. 18 is an enlarged view of an area EA3 of FIG. 17.

FIGS. 19, 20, 21, 22 and 23 are cross-sectional diagrams illustratingconductive patterns of a display device according to an embodiment ofthe present inventive concept.

DETAILED DESCRIPTION

Various modifications and changes may be applied to the examples ofembodiments in accordance with the concepts so that the examples ofembodiments will be illustrated in the drawings and described in thespecification. However, the examples of embodiments according to theconcepts are not limited to the specific embodiments, but include allchanges, equivalents, or alternatives which are included in the spiritand technical scope of the present disclosure.

Like reference numerals are used for referring to the same or similarelements in the description and drawings. In the attached drawings, thedimensions of the components exaggerated for clarity of illustration.Terminologies such as first or second may be used to describe variouscomponents but the components are not limited by the aboveterminologies. The above terminologies are used to distinguish onecomponent from the other component, for example, a first component maybe referred to as a second component without departing from a scope inaccordance with the concept of the present inventive concept andsimilarly, a second component may be referred to as a first component.The terms of a singular form may include plural forms unless referred tothe contrary.

In the present inventive concept, it will be appreciated that terms“including” and “having” are intended to designate the existence ofcharacteristics, numbers, steps, operations, constituent elements, andcomponents described in the specification or a combination thereof, anddo not exclude a possibility of the existence or addition of one or moreother specific characteristics, numbers, steps, operations, constituentelements, and components, or a combination thereof in advance. It willbe understood that when an element such as a layer, film, area, orsubstrate is referred to as being “on” another element, it can bedirectly on the other element or intervening elements may also bepresent. On the contrary, it will be understood that when an elementsuch as a layer, film, area, or substrate is referred to as being“beneath” another element, it can be directly beneath the other elementor intervening elements may also be present.

Hereinafter, aspects of some exemplary embodiments will be described inmore detail with reference to the accompanying drawings.

FIG. 1 is a perspective view illustrating a display device according toan embodiment. FIG. 2 is a plan view illustrating the display deviceshown in FIG. 1.

Referring to FIGS. 1 and 2, a display device according to an embodimentmay include a substrate SUB, pixels PXL provided on the substrate SUB,and wiring lines LP connected to the pixels PXL.

The substrate SUB may include a display area DA and a non-display areaNDA provided on at least one side of the display area DA.

The substrate SUB may have various shapes. For example, the substrateSUB may have a closed polygonal shape including straight sides. Inaddition, the substrate SUB may have a shape such as a circle and anellipse including a curved surface. In addition, the substrate SUB mayhave a semi-circular or semi-elliptical shape including curved andstraight sides. According to an embodiment, when the substrate SUBincludes straight sides, at least some of the corners of the angularshape may be curved. For example, when the substrate SUB has arectangular shape, a portion where adjacent straight sides meet may bereplaced by a curve having a predetermined curvature. In other words, avertex of the rectangular shape may include a curved side having bothadjacent sides connected to two adjacent straight sides and having apredetermined curvature. This curvature may vary depending on theposition. For example, the curvature may vary depending on the startposition of the curve starts and a length of the curve.

The substrate SUB may include the display area DA and the non-displayarea NDA. The pixels PXL displaying an image may be provided on thedisplay area DA. Each of the pixels PXL is described below. The pixelsPXL may not be provided on the non-display area NDA, where an image maynot be displayed. Some of the wiring lines LP connecting the pixels PXLto a driver COF may be provided on the non-display area NDA. Thenon-display area NDA may correspond to a bezel of the final displaydevice, and a width of the bezel may be determined depending on a widthof the non-display area NDA.

The plurality of pixels PXL may be provided on the display area DA,where an image may be displayed. The display area DA may have a shapecorresponding to the shape of the substrate SUB. For example, like theshape of the substrate SUB, the display area DA may have a closedpolygonal shape including straight sides. In addition, the display areaDA may have a circular or elliptical shape including a curved side. Thedisplay area DA may have a semi-circular or semi-elliptical shapeincluding straight and curved sides. According to an embodiment, whenthe display area DA has straight sides, at least some of the corners ofthe angular shape may be curved. For example, when the display area DAhas a rectangular shape, a portion where adjacent straight sides meetmay be replaced by a curve having a predetermined curvature. In otherwords, a vertex of the rectangular shape may include a curved sidehaving both adjacent ends connected to two adjacent straight lines andhaving a predetermined curvature. This curvature may vary depending onthe position. For example, the curvature may be changed depending on thestart position of the curve starts and a length of the curve.

The pixels PXL may be provided on the display area DA of the substrateSUB. Each of the pixels PXL may be a minimum unit for displaying animage. The plurality of pixels PXL may be provided on the display areaDA. The pixels PXL may emit white light and/or color light. For example,each pixel PXL may emit light of one of red, green, and blue. However,the inventive concept is not limited thereto. For example, each pixelPXL may also emit light of one of cyan, magenta and yellow.

The pixels PXL may be the basic unit for displaying an image and includevarious display elements (not illustrated). For example, each of thepixels PXL may include one of a liquid crystal (LCD) element, anelectrophoretic display (EPD) element, an electrowetting display (EWD)element, and an organic light emitting display (OLED) element.Hereinafter, for convenience of explanation, the OLED element isdescribed as an example of a display element OLED.

The wiring lines LP may connect the pixels PXL to the driver COF. Thedriver COF may provide signals to the respective pixels PXL through thewiring lines LP, thereby controlling the driving of each pixel PXL.

The driver COF may include a scan driver (not illustrated) providing ascan signal to the pixel PXL along a scan line (not illustrated), a datadriver providing a data signal to the pixel PXL along the data line (notillustrated), and a timing controller (not illustrated) controlling thescan driver and the data driver.

According to an embodiment, the scan driver may be directly formed onthe substrate SUB. When the scan driver is directly formed on thesubstrate SUB, the scan driver may be formed together at the same timewhen the pixels PXL are formed. However, the position and the method ofproviding the scan driver may not be limited thereto. For example, thescan driver may be formed in a separate chip and provided in achip-on-glass type on the substrate SUB, or the scan driver may beprovided on a printed circuit board (SUB), which may be connected to thesubstrate SUB by a connecting member.

According to an embodiment, the data driver may be directly formed onthe substrate SUB. However, the inventive concept is not limited. Forexample, the data drive may be formed in a separate chip and connectedto the substrate SUB. According to an embodiment, when the data driveris formed in the separate chip and connected to the substrate SUB, thedata driver may be provided using a chip-on-glass method or achip-on-plastic method. In another example, the data driver may beprovided on the printed circuit board (SUB) and connected to thesubstrate SUB by a connecting member. According to an embodiment, thedata driver may be manufactured as a chip-on-film type data driver,which may be connected to the substrate SUB.

According to an embodiment, the non-display area NDA may further includean additional area ADA extending from a portion thereof. The additionalarea ADA may protrude from sides forming the non-display area NDA. FIG.2 shows the additional area ADA protruding from a side corresponding toone of the short sides of the substrate SUB. However, the additionalarea ADA may also protrude from one of the long sides, or two or more ofthe four sides. According to an embodiment, the data driver may beprovided on or connected to the additional area ADA. However, theinventive concept is not limited thereto, and various components may beprovided on the additional area ADA.

According to an embodiment, a portion of the display device may haveflexibility and the display device may be folded at the flexibleportion. The display device may include a bent area BA that hasflexibility and is folded in one direction and a flat area FA which isprovided on at least one side of the bent area BA and is not folded. Theflat area FA may or may not have flexibility.

FIGS. 1 and 2 illustrate the bent area BA provided on the additionalarea ADA. According to an embodiment, a first flat area FA1 and a secondflat area FA2 may be provided at both sides of the bent area BA. Forexample, the first flat area FA1 may be provided at one side of the bentarea BA and the second flat area FA2 may be provided at the other sideof the bent area BA. The first flat area FA1 may include the displayarea DA.

In the bent area BA, when the display device is folded along a foldingline, the bending line may be provided in the bent area BA. The term“being fold” may mean that the shape is not fixed but may change fromthe original form to another form. When the display device is folded, itmay mean that the display is folded along at least one predeterminedfolding line, curved, or rolled up like a scroll. Therefore, accordingto an embodiment, it is illustrated that the display device is folded sothat respective surfaces of the two flat areas FA1 and FA2 may belocated in parallel and oppose each other. However, the inventiveconcept is not limited thereto. The display device may be folded so thatthe respective surfaces of the flat areas FA1 and FA2 may form apredetermined angle (e.g., an acute angle or an obtuse angle) with thebent area BA interposed therebetween.

According to an embodiment, the additional area ADA may be bent alongthe folding line. When the additional area ADA is bent, a width of thenon-display area NDA may be reduced, and the width of the display devicemay also be reduced.

FIG. 3 is an equivalent circuit diagram illustrating a pixel accordingto an embodiment. For convenience of explanation, FIG. 3 illustrates apixel connected to a jth data line Dj and an ith scan line Si.

Referring to FIG. 3, the pixel PXL may include the display element OLED,a first transistor T1, a second transistor T2, a third transistor T3, afourth transistor T4, a fifth transistor T5, a sixth transistor T6, aseventh transistor T7, and a storage capacitor Cst. According to anembodiment, the pixel PXL including seven thin film transistors and onestorage capacitor is illustrated an example. However, the inventiveconcept is not limited thereto. For example, the numbers of thin filmtransistors and storage capacitors included in the pixel PXL may bevariously changed. For example, the pixel PXL may include two thin filmtransistors and one storage capacitor. In another example, the pixel PXLmay include six thin film transistors and one storage capacitor.

An anode of the display element OLED may be connected to the firsttransistor T1 through the sixth transistor T6 and a cathode thereof maybe connected to a second power supply ELVSS. The OLED element OLED maygenerate light with predetermined brightness according to current flowsthrough the display element OLED.

A first power supply ELVDD may be set to a higher voltage than thesecond power supply ELVSS so that current may flow to the displayelement OLED.

The seventh transistor T7 may be connected between an initializationpower supply Vint and the anode of the display element OLED. A gateelectrode of the seventh transistor T7 may be connected to the ith scanline Si. The seventh transistor T7 may be turned on when a scan signalis supplied to the ith scan line Si, so that a voltage of theinitialization power supply Vint may be supplied to the anode of thedisplay element OLED. The initialization power supply Vint may be set toa lower voltage than a data signal.

The sixth transistor T6 may be connected between the first transistor T1and the display element OLED. A gate electrode of the sixth transistorT6 may be connected to an ith emission control line Ei. The sixthtransistor T6 may be turned off when a light emission control signal issupplied to the ith emission control line Ei and may be turned on duringthe remaining period.

The fifth transistor T1 may be connected between the first power supplyELVDD and the first transistor T1. A gate electrode of the fifthtransistor T5 may be connected to the ith emission control line Ei. Thefifth transistor T5 may be turned off when a light emission controlsignal is supplied to the ith emission control line Ei, and may beturned on during the remaining period.

A first electrode of the first transistor T1 (driving transistor) may beconnected to the first power supply ELVDD through the fifth transistorT5, and a second electrode thereof may be connected to the anode of thedisplay element OLED through the sixth transistor T6. A gate electrodeof the first transistor T1 may be connected to a first node N1. Thefirst transistor T1 may control the amount of current flowing from thefirst power supply ELVDD through the display element OLED to the secondpower supply ELVSS in response to a voltage of the first node N1. Inother words, the first power supply ELVDD may be electrically connectedto the anode of the display element OLED through the first transistorT1.

The third transistor T3 may be connected between the second electrode ofthe first transistor T1 and the first node N1. A gate electrode of thethird transistor T3 may be connected to the ith scan line Si. The thirdtransistor T3 may be turned on when the scan signal is supplied to theith scan line Si to electrically connect the second electrode of thefirst transistor T1 to the first node N1. Therefore, when the thirdtransistor T3 is turned on, the first transistor T1 may be connected inthe form of a diode.

The fourth transistor T4 may be connected between the first node N1 andthe initialization power supply Vint. A gate electrode of the fourthtransistor T4 may be connected to an (i−1)th scan line Si−1. The fourthtransistor T4 may be turned on when a scan signal is supplied to the(i−1)th scan line Si−1 to supply a voltage of the initialization powersupply Vint to the first node N1.

The second transistor T2 may be connected between the jth data line Djand the first electrode of the first transistor T1. The gate electrodeof the second transistor T2 may be connected to the ith scan line Si.The second transistor T2 may be turned on when the scan signal issupplied to the ith scan line Si to electrically connect the jth dataline Dj to the first electrode of the first transistor T1.

The storage capacitor Cst may be connected between the first powersupply ELVDD and the first node N1. The storage capacitor Cst may storevoltages corresponding to the data signal and a threshold voltage of thefirst transistor T1.

FIG. 4 is a detailed plan view of the pixel PXL shown in FIG. 3. FIG. 5is a cross-sectional diagram taken along the line II-II′ of FIG. 4. FIG.6 is a cross-sectional diagram taken along the line III-III′ of FIG. 4.

FIGS. 4 to 6 illustrate the two scan lines Si−1 and Si, the ith emissioncontrol line Ei, a power supply line PL, and the jth data line Djconnected to one pixel PXL arranged in an ith row and a jth column. InFIGS. 4 to 6, for convenience of explanation, a scan line in an (i−1)throw is referred to as an “(i−1)th scan line Si−1”, a scan line in an ithrow is referred to as an “ith scan line Si”, an emission control line inthe ith row is referred to as an “emission control line Ei”, a data linein the jth column is referred to as a “data line Dj”, and a jth powersupply line is referred to as a “power supply line PL.”.

Referring to FIGS. 1 to 6, the display device may include the substrateSUB and the pixels PXL.

The substrate SUB may include a transparent insulating material totransmit light. The substrate SUB may be a rigid substrate. For example,the substrate SUB may be one of a glass substrate, a quartz substrate, aglass ceramic substrate and a crystalline glass substrate.

In addition, the substrate SUB may be a flexible substrate. Thesubstrate SUB may be one of a plastic substrate and a film substrateincluding a polymer organic material. For example, the substrate SUB mayinclude at least one of polystyrene, polyvinyl alcohol, polymethylmethacrylate, polyethersulfone, polyacrylate, polyetherimide,polyethylene naphthalate, polyethylene terephthalate, polyphenylenesulfide, polyarylate, polyimide, polycarbonate, triacetate cellulose,and cellulose acetate propionate. The material forming the substrate SUBmay be variously changed and include fiber reinforced plastic (FRP).

The pixels PXL may be connected to the scan lines Si−1 and Si, the dataline Dj, the emission control line Ei, the power supply line PL, and aninitialization power supply line IPL.

The scan lines Si−1 and Si may extend in a first direction DR1. The scanlines Si−1 and Si may include the (i−1)th scan line Si−1 and two ithscan lines Si arranged sequentially in a second direction DR2. Scansignals may be supplied to the scan lines Si−1 and Si. For example, an(i−1)th scan signal may be supplied to the (i−1)th scan line Si−1. The(i−1)th scan line Si−1 may initialize the pixels PXL in the ith row inresponse to the (i−1)th scan signal. An ith scan signal may be appliedto the ith scan lines Si. The first scan lines Si may be branched offfrom one line connected to the scan driver and may be connected todifferent transistors. For example, one of the ith scan lines Si may beconnected to the second transistor T2 and the third transistor T3, amongthe first to seventh transistors T1 to T7 included in the pixels PXL,and the other may be connected to the seventh transistor T7, among thefirst to seventh transistors T1 to T7. In addition, a branch point ofthe first scan lines Si may be provided in the non-display area NDAadjacent to the display area DA. However, the inventive concept is notlimited thereto. For example, the branch point of the first scan linesSi may be provided in the display area DA at a position adjacent to thenon-display area NDA.

The emission control line Ei may extend in the first direction DR1. Theemission control line Ei may be interposed between and separated fromthe two ith scan lines Si. A light emission control signal may beapplied to the emission control line Ei.

The power supply line PL may extend in the second direction DR2. Thepower supply line PL may be separated from the data line Dj. The firstpower supply ELVDD may be applied to the power supply line PL.

The initialization power supply line IPL may extend in the firstdirection DR1. The initialization power supply line IPL may be providedbetween the pixel PXL in the ith pixel row and the pixel PXL in the(i+1)th pixel row. The initialization power supply Vint may be appliedto the initialization power supply line IPL.

Each of the pixels PXL may include the first to seventh transistors T1to T7, the storage capacitor Cst, and the display element OLED.

The first transistor T1 may include a first gate electrode GE1, a firstactive pattern ACT1, a first source electrode SE1, a first drainelectrode DE1, and a connection line CNL.

The first gate electrode GE1 may be connected to a third drain electrodeDE3 of the third transistor T3 and a fourth drain electrode DE4 of thefourth transistor T4. The connection line CNL may connect the first gateelectrode GE1, the third drain electrode DE3 and the fourth drainelectrode DE4 to each other. One end of the connection line CNL may beconnected to the first gate electrode GE1 through a first contact holeCH1, and the other end of the connection line CNL may be connected tothe third drain electrode DE3 and the fourth drain electrode DE4 througha second contact hole CH2.

According to an embodiment, each of the first active pattern ACT1, thefirst source electrode SE1, and the first drain electrode DE1 mayinclude a semiconductor layer doped or undoped with impurities. Forexample, each of the first source electrode SE1 and the first drainelectrode DE1 may include a semiconductor layer doped with impuritiesand the first active pattern ACT1 may include a semiconductor layerundoped with impurities.

The first active pattern ACT1 may have a bar shape extending in apredetermined direction and be bent several times in the extended lengthdirection. As viewed in the plane, the first active pattern ACT1 mayoverlap with the first gate electrode GE1. Since the first activepattern ACT1 extends in the predetermine direction, a channel region ofthe first transistor T1 may also extend in the predetermined direction,thus, the channel length of the first transistor T1 may be long.Therefore, a driving range of a gate voltage applied to the firsttransistor T1 may be broadened. Therefore, minute grayscale control oflight emitted from the display element OLED may be allowed.

The first source electrode SE1 may be connected to one end of the firstactive pattern ACT1. The first source electrode SE1 may be connected toa second drain electrode DE2 of the second transistor T2 and a fifthdrain electrode DE5 of the fifth transistor T5. The first drainelectrode DE1 may be connected to the other end of the first activepattern ACT1. The first drain electrode DE1 may be connected to a thirdsource electrode SE3 of the third transistor T3 and a sixth sourceelectrode SE6 of the sixth transistor T6.

The second transistor T2 may include a second gate electrode GE2, asecond active pattern ACT2, a second source electrode SE2, and a seconddrain electrode DE2.

The second gate electrode GE2 may be connected to the ith scan line Si.The second gate electrode GE2 may be provided as a portion of the ithscan line Si, or may protrude from the ith scan line Si. According to anembodiment, each of the second active pattern ACT2, the second sourceelectrode SE2 and the second drain electrode DE2 may include asemiconductor layer doped or undoped with impurities. For example, eachof the second source electrode SE2 and the second drain electrode DE2may include a semiconductor layer doped with impurities and the secondactive pattern ACT2 may be a semiconductor layer undoped withimpurities. The second active pattern ACT2 may correspond to anoverlapping portion between the second source and drain electrodes SE2and DE2 and the second gate electrode GE2. One end of the second sourceelectrode SE2 may be connected to the second active pattern ACT2 and theother end of the second source electrode SE2 may be connected to thedata line Dj through a sixth contact hole CH6. One end of second drainelectrode DE2 may be connected to the second active pattern ACT2 and theother end thereof may be connected to the first source electrode SE1 ofthe first transistor T1 and the fifth drain electrode DE5 of the fifthtransistor T5.

The third transistor T3 may be provided as a dual gate structure toprevent current leakage. In other words, the third transistor T3 mayinclude a 3a-th transistor T3 a and a 3b-th transistor T3 b. The 3a-thtransistor T3 a may include a 3a-th gate electrode GE3 a, a 3a-th activepattern ACT3 a, a 3a-th source electrode SE3 a, and a 3a-th drainelectrode DE3 a. The 3b-th transistor T3 b may include a 3b-th gateelectrode GE3 b, a 3b-th active pattern ACT3 b, a 3b-th source electrodeSE3 b, and a 3b-th drain electrode DE3 b. Hereinafter, the 3a-th gateelectrode GE3 a and the 3b-th gate electrode GE3 b are referred to as a“third gate electrode GE3”, the 3a-th active pattern ACT3 a and the3b-th active pattern ACT3 b are referred to as a “third active patternACT3”, the 3a-th source electrode SE3 a and the 3b-th source electrodeSE3 b are referred to as a “third source electrode SE3”, and the 3a-thdrain electrode DE3 a and the 3b-th drain electrode DE3 b are referredto as a “third drain electrode DE3”.

The third gate electrode GE3 may be connected to the ith scan line Si.The third gate electrode GE3 may be provided as a portion of the ithscan line Si, or protrude from the ith scan line Si. For example, the3a-th gate electrode GE3 a may protrude from the ith scan line Si, andthe 3b-th gate electrode GE3 b may be provided as a portion of the ithscan line Si.

Each of the third active pattern ACT3, the third source electrode SE3and the third drain electrode DE3 may include a semiconductor layerdoped or undoped with impurities. For example, each of the third sourceelectrode SE3 and the third drain electrode DE3 may include asemiconductor layer doped with impurities and the third active patternACT3 may include a semiconductor layer undoped with impurities. Thethird active pattern ACT3 may correspond to an overlapping portionbetween the third source and drain electrodes SE3 and DE3 and the thirdgate electrode GE3. One end of the third source electrode SE3 may beconnected to the third active pattern ACT3 and the other end thereof maybe connected to the first drain electrode DE1 of the first transistor T1and the sixth source electrode SE6 of the sixth transistor T6. One endof the third drain electrode DE3 may be connected to the third activepattern ACT3. The other end of the third drain electrode DE3 may beconnected to the fourth drain electrode DE4 of the fourth transistor T4.In addition, the third drain electrode DE3 may be connected to the firstgate electrode GE1 of the first transistor T1 through the connectionline CNL, the second contact hole CH2 and the first contact hole CH1.

The fourth transistor T4 may have a dual gate structure to preventcurrent leakage. In other words, the fourth transistor T4 may include a4a-th transistor and a 4b-th transistor. The 4a-th transistor T4 mayinclude a 4a-th gate electrode GE4 a, a 4a-th active pattern ACT4 a, a4a-th source electrode SE4 a, and a 4a-th drain electrode DE4 a. The4b-th transistor may include a 4b-th gate electrode GE4 b, a 4b-thactive pattern ACT4 b, a 4b-th source electrode SE4 b, and a 4b-th drainelectrode DE4 b. Hereinafter, the 4a-th gate electrode GE4 a and the4b-th gate electrode GE4 b are referred to as a “fourth gate electrodeGE4”, the 4a-th active pattern ACT4 a and the 4b-th active pattern ACT4b are referred to as a “fourth active pattern ACT4”, the 4a-th sourceelectrode SE4 a and the 4b-th source electrode SE4 b are referred to asa “fourth source electrode SE4”, and the 4a-th drain electrode DE4 a andthe 4b-th drain electrode DE4 b are referred to as a “fourth drainelectrode DE4”.

The fourth gate electrode GE4 may be connected to the (i−1)th scan lineSi−1. The fourth gate electrode GE4 may be provided as a portion of the(i−1)th scan line Si−1, or may protrude from the (i−1)th scan line Si−1.For example, the 4a-th gate electrode GE4 a may be provided as a portionof the (i−1)th scan line Si−1. The 4b-th gate electrode GE4 b may extendfrom the (i−1)th scan line Si−1.

Each of the fourth active pattern ACT4, each of the fourth sourceelectrode SE4 and the fourth drain electrode DE4 may include asemiconductor layer doped or undoped with impurities. For example, eachof the fourth source electrode SE4 and the fourth drain electrode DE4may include a semiconductor layer doped with impurities and the fourthactive pattern ACT4 may include a semiconductor layer undoped withimpurities. The fourth active pattern ACT4 may correspond to anoverlapping portion between the fourth source and drain electrodes SE4and DE4 and the fourth gate electrode GE4.

One end of the fourth source electrode SE4 may be connected to thefourth active pattern ACT4 and the other end of the fourth sourceelectrode SE4 may be connected to the initialization power supply lineIPL of the pixel PXL in the (i−1)th row and a seventh drain electrodeDE7 of the seventh transistor T7 in the pixel PXL in the (i−1)th row. Anauxiliary connection line AUX may be provided between the fourth sourceelectrode SE4 and the initialization power supply line IPL. One end ofthe auxiliary connection line AUX may be connected to the fourth sourceelectrode SE4 through a ninth contact hole CH9. The other end of theauxiliary connection line AUX may be connected to the initializationpower supply line IPL in the (i−1)th row through an eighth contact holeCH8 of the pixel PXL in the (i−1)th row. One end of the fourth drainelectrode DE4 may be connected to the fourth active pattern ACT4. Theother end of the fourth drain electrode DE4 may be connected to thethird drain electrode DE3 of the third transistor T3. The fourth drainelectrode DE4 may be connected to the first gate electrode GE1 of thefirst transistor T1 through the connection line CNL, the second contacthole CH2 and the first contact hole CH1.

The fifth transistor T5 may include a fifth gate electrode GE5, a fifthactive pattern ACT5, a fifth source electrode SE5, and the fifth drainelectrode DE5.

The fifth gate electrode GE5 may be connected to the emission controlline Ei. The fifth gate electrode GE5 may be provided as a portion ofthe emission control line Ei and protrude from the emission control lineEi. Each of the fifth active pattern ACT5, the fifth source electrodeSE5 and the fifth drain electrode DE5 may be a semiconductor layer dopedor undoped with impurities. For example, each of the fifth sourceelectrode SE5 and the fifth drain electrode DE5 may include asemiconductor layer doped with impurities and the fifth active patternACT5 may include a semiconductor layer undoped with impurities. Thefifth active pattern ACT5 may correspond to an overlapping portionbetween the fifth source and drain electrodes SE5 and DE5 and the fifthgate electrode GE5. One end of the fifth source electrode SE5 may beconnected to the fifth active pattern ACT5. The other end of the fifthsource electrode SE5 may be connected to the power supply line PLthrough a fifth contact hole CH5. One end of the fifth drain electrodeDE5 may be connected to the fifth active pattern ACT5. The other end ofthe fifth drain electrode DE5 may be connected to the first sourceelectrode SE1 of the first transistor T1 and the second drain electrodeDE2 of the second transistor T2.

The sixth transistor T6 may include a sixth gate electrode GE6, a sixthactive pattern ACT6, the sixth source electrode SE6, and a sixth drainelectrode DE6.

The sixth gate electrode GE6 may be connected to the emission controlline Ei. The sixth gate electrode GE6 may be provided as the emissioncontrol line Ei or protrude from the emission control line Ei. Each ofthe sixth active pattern ACT6, the sixth source electrode SE6 and thesixth drain electrode DE6 may include a semiconductor layer doped orundoped with impurities. For example, each of the sixth source electrodeSE6 and the sixth drain electrode DE6 may include a semiconductor layerdoped with impurities and the sixth active pattern ACT6 may include asemiconductor layer undoped with impurities. The sixth active patternACT6 may correspond to an overlapping portion between the sixth sourceand drain electrodes SE6 and DE6 and the sixth gate electrode GE6. Oneend of the sixth source electrode SE6 may be connected to the sixthactive pattern ACT6. The other end of the sixth source electrode SE6 maybe connected to the first drain electrode DE1 of the first transistor T1and the third source electrode SE3 of the third transistor T3. One endof the sixth drain electrode DE6 may be connected to the sixth activepattern ACT6. The other end of the sixth drain electrode DE6 may beconnected to a seventh source electrode SE7 of the seventh transistorT7.

The seventh transistor T7 may include a seventh gate electrode GE7, aseventh active pattern ACT7, the seventh source electrode SE7, and theseventh drain electrode DE7.

The seventh gate electrode GE7 may be connected to the ith scan line Si.The seventh gate electrode GE7 may be provided as a portion of the ithscan line Si or extend from the ith scan line Si. Each of the seventhactive pattern ACT7, the seventh source electrode SE7 and the seventhdrain electrode DE7 may include a semiconductor layer doped or undopedwith impurities. For example, each of the seventh source electrode SE7and the seventh drain electrode DE7 may include a semiconductor layerdoped with impurities and the seventh active pattern ACT7 may include asemiconductor layer undoped with impurities. The seventh active patternACT7 may correspond to an overlapping portion between the seventh sourceand drain electrodes SE7 and DE7 and the seventh gate electrode GE7. Oneend of the seventh source electrode SE7 may be connected to the seventhactive pattern ACT7. The other end of the seventh source electrode SE7may be connected to the sixth drain electrode DE6 of the sixthtransistor T6. One end of the seventh drain electrode DE7 may beconnected to the seventh active pattern ACT7. The other end of theseventh drain electrode DE7 may be connected to the initialization powersupply line IPL. In addition, the seventh drain electrode DE7 may beconnected to the fourth source electrode SE4 of the fourth transistor T4of the pixel PXL in the (i+1)th row. The seventh drain electrode DE7 andthe fourth source electrode SE4 of the fourth transistor T4 of the pixelPXL in the (i+1)th row may be connected through the auxiliary connectionline AUX, the eighth contact hole CH8, and the ninth contact hole CH9.

The storage capacitor Cst may include a lower electrode LE and an upperelectrode UE. The lower electrode LE may include the first gateelectrode GE1 of the first transistor T1.

The upper electrode UE may overlap with the first gate electrode GE1 andcover the lower electrode LE in a plan view. The capacitance of thestorage capacitor Cst may be increased by increasing an overlapping areabetween the upper electrode UE and the lower electrode LE. The upperelectrode UE may extend in the first direction DR1. According to anembodiment, a voltage having the same voltage level as the first powersupply ELVDD may be applied to the upper electrode UE. The upperelectrode UE may be opened by removing a portion of a region where thefirst contact hole CH1 in contact with the first gate electrode GE1 andthe connection line CNL is formed.

The display element OLED may include a first electrode AD, a secondelectrode CD, and an emitting layer EML provided between the firstelectrode AD and the second electrode CD.

The first electrode AD may be provided in an emission area correspondingto each pixel PXL. The first electrode AD may be connected to theseventh source electrode SE7 of the seventh transistor T7 and the sixthdrain electrode DE6 of the sixth transistor T6 through the seventhcontact hole CH7 and a tenth contact hole CH10, respectively. The firstbridge pattern BRP1 may be provided between the seventh contact hole CH7and the tenth contact hole CH10. A second bridge pattern BRP2 may beprovided between the tenth contact hole CH10 and a twelfth contact holeCH12. The first bridge pattern BRP1 and the second bridge pattern BRP2may connect the sixth drain electrode DE6, the seventh source electrodeSE7 and the first electrode AD.

Hereinafter, the structure of the display element OLED according to anembodiment is described according to a stacking order with reference toFIGS. 4 to 6.

The first to seventh active patterns ACT1 to ACT7 may be provided on thesubstrate SUB. The first to seventh active patterns ACT1 to ACT7 mayinclude a semiconductor material.

A buffer layer BUL may be provided between the substrate SUB and thefirst to seventh active patterns ACT1 to ACT7. The buffer layer BUL mayprevent impurities from being diffused from the substrate SUB into thefirst to seventh active patterns ACT1 to ACT7. The buffer layer BUL maybe formed in a single layer. However, the buffer layer BUL may have amultilayer structure including at least two layers. The buffer layer BULmay include at least one of an organic insulating layer and an inorganicinsulating layer. The organic insulating layer may include an organicinsulating material capable of transmitting light. The inorganicinsulating layer may include at least one of silicon oxide, siliconnitride and silicon oxynitride. When the buffer layer BUL has amultilayer structure, the respective layers may include the same ordifferent materials from each other. For example, the inorganicinsulating layer may include a first layer including a silicon oxide anda second layer provided on the first layer and including a siliconnitride.

A gate insulating layer GI may be provided over the substrate SUB onwhich the first to seventh active patterns ACT1 to ACT7 are formed. Thegate insulating layer GI may include at least one of an organicinsulating layer and an inorganic insulating layer. The organicinsulating layer may include an organic insulating material capable oftransmitting light. For example, the organic insulating layer mayinclude at least one of photoresist, polyacrylates resin, epoxy resin,phenolic resin, polyamides resin, polyimides resin, unsaturatedpolyesters resin, poly-phenylene ethers resin, poly-phenylene sulfidesresin, and benzocyclobutenes resin. The inorganic insulating layer mayinclude at least one of silicon oxide, silicon nitride and siliconoxynitride.

The (i−1)th scan line Si−1, the ith scan line Si, the emission controlline Ei, and the first to seventh gate electrodes GE1 to GE7 may beprovided on the gate insulating layer GI. The first gate electrode GE1may be the lower electrode LE of the storage capacitor Cst. The secondgate electrode GE2 and the third gate electrode GE3 may be formedintegrally with the ith scan line Si. The fourth gate electrode GE4 maybe formed integrally with the (i−1)th scan line Si−1. The fifth gateelectrode GE5 and the sixth gate electrode GE6 may be formed integrallywith the emission control line Ei. The seventh gate electrode GE7 may beformed integrally with the ith scan line Si.

Each of the (i−1)th scan line Si−1, the ith scan line Si, the emissioncontrol line Ei, and the first to seventh gate electrodes GE1 to GE7 mayinclude a metallic material. For example, the (i−1)th scan line Si−1,the ith scan line Si, the emission control line Ei, and the first toseventh gate electrodes GE1 to GE7 may include at least one of gold(Au), silver (Ag), aluminum (Al), molybdenum (Mo), chromium (Cr),titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and an alloythereof. Each of the (i−1)th scan line Si−1, the ith scan line Si, theemission control line Ei, and the first to seventh gate electrodes GE1to GE7 may be formed in a single layer. However, the inventive conceptis not limited thereto. For example, each of the (i−1)th scan line Si−1,the ith scan line Si, the emission control line Ei, and the first toseventh gate electrodes GE1 to GE7 may have a multilayer structure oftwo or more layers including at least one of gold (Au), silver (Ag),aluminum (Al), molybdenum (Mo), chromium (Cr), titanium (Ti), nickel(Ni), neodymium (Nd), copper (Cu), and an alloy thereof.

A first interlayer insulating layer IL1 may be provided over thesubstrate SUB on which the (i−1)th scan line Si−1 is formed. The firstinterlayer insulating layer IL1 may include at least one ofpolysiloxane, silicon oxide, silicon nitride and silicon oxynitride.

The upper electrode UE of the storage capacitor Cst and theinitialization power supply line IPL may be provided on the firstinterlayer insulating layer IL1. The upper electrode UE may overlap thelower electrode LE. The upper electrode UE and the lower electrode LEmay form the storage capacitor Cst with the first interlayer insulatinglayer IL1 interposed therebetween. Each of the upper electrode UE andthe initialization power supply line IPL may include gold (Au), silver(Ag), aluminum (Al), molybdenum (Mo), chromium (Cr), titanium (Ti),nickel (Ni), neodymium (Nd), copper (Cu), and an alloy thereof. Each ofthe upper electrode UE and the initialization power supply line IPL maybe formed in a single layer. However, the inventive concept is notlimited thereto. For example, each of the upper electrode UE and theinitialization power supply line IPL may have a multilayer structure oftwo or more layers including at least one of gold (Au), silver (Ag),aluminum (Al), molybdenum (Mo), chromium (Cr), titanium (Ti), nickel(Ni), neodymium (Nd), copper (Cu), and an alloy thereof.

A second interlayer insulating layer IL2 may be provided over thesubstrate SUB where the upper electrode UE and the initialization powersupply line IPL are arranged.

The second interlayer insulating layer IL2 may include at least one ofan inorganic insulating layer and an organic insulating layer. Forexample, the second interlayer insulating layer IL2 may include at leastone inorganic insulating layer. The inorganic insulating layer mayinclude at least one of silicon oxide, silicon nitride and siliconoxynitride. In addition, the second interlayer insulating layer IL2 mayinclude at least one organic insulating layer. The organic insulatinglayer may include photoresist, polyacrylates resin, epoxy resin,phenolic resin, polyamides resin, polyimides resin, unsaturatedpolyesters resin, poly-phenylene ethers resin, poly-phenylene sulfidesresin, and benzocyclobutenes resin. In addition, the second interlayerinsulating layer IL2 may have a multilayer structure including at leastone inorganic insulating layer and at least one organic insulatinglayer.

First conductive patterns may be provided on the second interlayerinsulating layer IL2. The first conductive patterns may include the dataline Dj, the connection line CNL, the auxiliary connection line AUX, thefirst bridge pattern BRP1, and the power supply line PL.

The data line Dj may be connected to the second source electrode SE2through the sixth contact hole CH6 passing through the first interlayerinsulating layer IL1, the second interlayer insulating layer IL2, andthe gate insulating layer GI.

The connection line CNL may be connected to the first gate electrode GE1through the first contact hole CH1 passing through the first interlayerinsulating layer IL1 and the second interlayer insulating layer IL2. Inaddition, the connection line CNL may be connected to the third drainelectrode DE3 and the fourth drain electrode DE4 through the secondcontact hole CH2 passing through the gate insulating layer GI, the firstinterlayer insulating layer IL1 and the second interlayer insulatinglayer IL2.

The auxiliary connection line AUX may be connected to the initializationpower supply line IPL through the eighth contact hole CH8 passingthrough the second interlayer insulating layer IL2. In addition, theauxiliary connection line AUX may be connected to the fourth sourceelectrode SE4 and the seventh drain electrode DE7 of the pixel PXL inthe (i−1)th row through the ninth contact hole CH9 passing through thegate insulating layer GI, the first interlayer insulating layer IL1, andthe second interlayer insulating layer IL2.

The first bridge pattern BRP1 may be provided between the sixth drainelectrode DE6 and the first electrode AD and serve as a medium forconnecting the sixth drain electrode DE6 and the first electrode AD toeach other. The first bridge pattern BRP1 may be connected to the sixthdrain electrode DE6 and the first source electrode SE1 through theseventh contact hole CH7 passing through the gate insulating layer GI,the first interlayer insulating layer IL1, and the second interlayerinsulating layer IL2.

A third interlayer insulating layer IL3 may be provided over thesubstrate SUB on which the first conductive patterns are provided. Thethird interlayer insulating layer IL3 may include a first insulatinglayer IL31 and a second insulating layer IL32 provided on the firstinsulating layer IL31.

The first insulating layer IL31 may include an inorganic insulatingmaterial. For example, the first insulating layer IL31 may include atleast one of polysiloxane, silicon oxide, silicon nitride and siliconoxynitride.

The second interlayer insulating layer IL2 may include an inorganicinsulating material. For example, the second interlayer insulating layerIL2 may include at least one inorganic insulating layer. The inorganicinsulating material may include at least one of silicon oxide, siliconnitride and silicon oxynitride. In addition, the second insulating layerIL32 may include an organic insulating material. For example, the secondinsulating layer IL32 may include at least one of photoresist,polyacrylates resin, epoxy resin, phenolic resin, polyamides resin,polyimides resin, unsaturated polyesters resin, poly-phenylene ethersresin, poly-phenylene sulfides resin, and benzocyclobutenes resin. Inaddition, the second interlayer insulating layer IL2 may have amultilayer structure including at least one inorganic insulating layerand at least one organic insulating layer.

Second conductive patterns may be provided on the third interlayerinsulating layer IL3. The second conductive patterns may include thepower supply line PL and the second bridge pattern BRP2. The secondbridge pattern BRP2 may be connected to the first bridge pattern BRP1through the tenth contact hole CH10 passing through the first insulatinglayer IL3 and the third interlayer insulating layer IL3.

The power supply line PL may be connected to the upper electrode UE ofthe storage capacitor Cst through the third and fourth contact holes CH3and CH4 passing through the second interlayer insulating layer IL2 andthe third interlayer insulating layer IL3. The power supply line PL maybe connected to the fifth source electrode SE5 through the fifth contacthole CH5 passing through the first interlayer insulating layer IL1, thesecond interlayer insulating layer IL2, the third interlayer insulatinglayer IL3, and the gate insulating layer GI.

A fourth interlayer insulating layer IL4 may be provided on the thirdinterlayer insulating layer IL3 on which the second conductive patternsare provided.

The fourth interlayer insulating layer IL4 may include an organicinsulating material. For example, the fourth interlayer insulating layerIL4 may include at least one of photoresist, polyacrylates resin, epoxyresin, phenolic resin, polyamides resin, polyimides resin, unsaturatedpolyesters resin, poly-phenylene ethers resin, poly-phenylene sulfidesresin, and benzocyclobutenes resin.

The display element OLED may be provided on the fourth interlayerinsulating layer IL4. The display element OLED may include the firstelectrode AD, the second electrode CD, and the emitting layer EMLprovided between the first electrode AD and the second electrode CD.

The first electrode AD may be provided on the fourth interlayerinsulating layer IL4. The first electrode AD may be connected to thesecond bridge pattern BRP2 through the twelfth contact hole CH12 passingthrough the fourth interlayer insulating layer IL4. Therefore, the firstelectrode AD may be electrically connected to the first bridge patternBRP1. The first bridge pattern BRP1 may be connected to the sixth drainelectrode DE6 and the seventh source electrode SE7 through the seventhcontact hole CH7. Therefore, the first electrode AD may be finallyconnected to the sixth drain electrode DE6 and the seventh sourceelectrode SE7.

A pixel defining layer PDL defining an emission area so as to correspondto each pixel PXL may be provided over the substrate SUB where the firstelectrode AD is formed. The pixel defining layer PDL may expose an uppersurface of the first electrode AD and protrude from the substrate SUBalong the circumference of the pixel PXL. However, according to anotherembodiment, the first electrode AD may be formed over the pixel defininglayer PDL.

The emitting layer EML may be provided on the emission area surroundedby the pixel defining layer PDL, and the second electrode CD may beprovided on the emitting layer EML. A sealing layer SLM may be providedon the second electrode CD to cover the second electrode CD.

One of the first electrode AD and the second electrode CD may be ananode electrode and the other may be a cathode electrode. For example,the first electrode AD may be an anode electrode, and the secondelectrode CD may be cathode electrode.

In addition, at least one of the first electrode AD and the secondelectrode CD may be a transmissive electrode. For example, when thedisplay element OLED is a bottom emission type organic light emittingdevice, the first electrode AD may be a transmissive electrode and thesecond electrode CD may be a reflective electrode. When the displayelement OLED is a top emission type organic light emitting device, thefirst electrode AD may be a reflective electrode and the secondelectrode CD may be a transmissive electrode. When the display elementOLED is a dual emission type organic light emitting device, both thefirst electrode AD and the second electrode CD may be transmissiveelectrodes. According to an embodiment, for example, the display elementOLED may be a top emission type organic light emitting device and thefirst electrode AD may be an anode electrode.

The first electrode AD may include a reflective layer (not illustrated)capable of reflecting light and a transparent conductive layer (notillustrated) provided above or under the reflective layer. At least oneof the transparent conductive layer and the reflective layer may beelectrically connected to the seventh source electrode SE7.

The reflective layer may include a light reflecting material. Forexample, the reflective layer may include at least one of aluminum (Al),silver (Ag), chromium (Cr), molybdenum (Mo), platinum (Pt), nickel (Ni)and an alloy thereof.

The transparent conductive layer may include a transparent conductiveoxide. For example, the transparent conductive layer may include atleast one transparent conductive oxide, among Indium Tin Oxide (ITO),Indium Zinc Oxide (IZO), Aluminum Zinc Oxide (AZO), gallium doped zincoxide (GZO), zinc tin oxide (ZTO), Gallium tin oxide (GTO) and fluorinedoped tin oxide (FTO).

The pixel defining layer PDL may include an organic insulating material.For example, the pixel defining layer PDL may include at least one ofpolystyrene, polymethylmethacrylate (PMMA), polyacrylonitrile (PAN),polyamide (PA), polyimide (P), polyarylether (PAE), heterocyclicpolymer, parylene, epoxy, benzocyclobutene (BCB), siloxane based resinand silane based resin.

The emitting layer EML may be arranged on the exposed surface of thefirst electrode AD. The emitting layer EML may have a multilayer filmstructure including at least a light generation layer LGL. For example,the emitting layer EML may include a hole injection layer HIL injectingholes, a hole transport layer HTL having excellent hole transportabilityand increasing recombination between holes and electrons by blockingmovements of electrons which fail to be combined in the light generationlayer LGL, the light generation layer LGL generating light byrecombination of the injected electrons and holes, a hole blocking layerHBL blocking the movements of the holes which fail to be combined in thelight generation layer LGL, an electron transport layer ETL smoothlytransporting electrons to the light generation layer LGL, and anelectron injection layer EIL injecting electrons. In addition, the holeinjection layer, the hole transport layer, the hole blocking layer, theelectron transport layer, and the hole injection layer included in theemitting layer EML may be common layers that are commonly arranged inneighboring pixels PXL.

Color of light generated from the light generation layer may be one ofred, green, blue and white. However, the inventive concept is notlimited thereto. For example, the light generation layer may be one ofmagenta, cyan, and yellow.

The second electrode CD may be a transflective layer. For example, thesecond electrode CD may be a thin metal layer which is thin enough totransmit light emitted from the emitting layer EML. The second electrodeCD may transmit part of the light emitted from the emitting layer EMLand reflect the rest of the light emitted from the emitting layer EML.

The second electrode CD may include a material having a lower workfunction than the transparent conductive layer. For example, the secondelectrode CD may include at least one of molybdenum (Mo), tungsten (W),silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium(Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium(Cr), lithium (Li), calcium (Ca) and an alloy thereof.

Part of the light emitted from the emitting layer EML may not transmitthe second electrode CD and light reflected from the second electrode CDmay be reflected from the reflective layer again. In other words, thelight emitted from the emitting layer EML may resonate between thereflective layer and the second electrode CD. The resonance of the lightmay contribute to improvement of light extraction efficiency of thedisplay devices OLED.

The distance between the reflective layer and the second electrode CDmay vary depending on the color of the light emitted from the emittinglayer EML. In other words, the distance between the reflective layer andthe second electrode CD may be adjusted to correspond to the resonancedistance in accordance with the color of the light emitted from theemitting layer EML.

The sealing layer SLM may prevent intrusion of oxygen and moisture intothe display element OLED. The sealing layer SLM may include a pluralityof inorganic layers (not illustrated) and a plurality of organic layers(not illustrated). For example, the sealing layer SLM may include aplurality of unit sealing layers consisting of an inorganic layer and anorganic layer arranged on the inorganic layer. In addition, an inorganiclayer may be arranged on a top portion of the sealing layer SLM. Theinorganic layer may include at least one of silicon oxide, siliconnitride, silicon oxynitride, aluminum oxide, titanium oxide, zirconiumoxide and tin oxide.

FIGS. 7A and 7B are enlarged views of the area EA1 of FIG. 5. FIGS. 8Aand 8B are enlarged views of the area EA2 of FIG. 7. FIGS. 9 to 12 areelectron microscopic images showing a conductive pattern formed on anorganic layer including polyimide. FIGS. 13 to 16 are high-angle annulardark-field (HAADF) images showing a conductive pattern formed on anorganic layer including polyimide. The conductive pattern shown in FIGS.9, 10, 13 and 14 may include a titanium (Ti) layer and an aluminum (Al)layer sequentially stacked on an insulating layer. The conductivepattern shown in FIGS. 11 and 15 may include a titanium nitride (TIN)layer, a titanium (Ti) layer, and an aluminum (Al) layer sequentiallystacked on an insulating layer. The conductive pattern shown in FIGS. 12and 16 may include a titanium nitride (TiN) layer and an aluminum (Al)layer sequentially stacked on an insulating layer.

Referring to FIGS. 4 to 16, each pixel PXL may include at least onetransistor provided on the substrate SUB, the display element OLEDconnected to the transistor, and the first bridge pattern BRP1 and thesecond bridge pattern BRP2 connecting the transistor to the displayelement OLED.

The transistor may be covered by the first interlayer insulating layerIL1 and the second interlayer insulating layer IL2. The first bridgepattern BRP1 connected to the data line Dj, the connection line CNL, andthe transistor may be provided on the second interlayer insulating layerIL2. The data line Dj, the connection line CNL, and the first bridgepattern BRP1 may be one of the first conductive patterns provided on thesecond interlayer insulating layer IL2.

The second interlayer insulating layer IL2 may include an inorganicinsulating material. For example, the second interlayer insulating layerIL2 may include at least one inorganic insulating layer. The inorganicinsulating material may include at least one of silicon oxide, siliconnitride and silicon oxynitride. In addition, the second insulating layerIL32 may also include an organic insulating material. The organicinsulating material may be at least one of polyacrylates resin, epoxyresin, phenolic resin, polyamides resin, polyimides rein, unsaturatedpolyesters resin, poly-phenylene ethers resin, poly-phenylene sulfidesresin, and benzocyclobutenes resin. All the above described-materialsincluded in the organic insulating layer may include carbon and oxygen.In addition, the organic insulating material may further include atleast one of oxygen, nitrogen, fluorine, and sulfur.

The first conductive patterns, for example, the first bridge patternBRP1 may further include a 1A-th conductive layer CL1A. In addition,when the second interlayer insulating layer IL2 includes an organicinsulating material, the first conductive patterns may further include a2A-th conductive layer CL2A provided between the second interlayerinsulating layer IL2 and the 1A-th conductive layer CL1A.

The 1A-th conductive layer CL1A may include a first sub-conductive layerSCL1 provided on the second interlayer insulating layer IL2 and a secondsub-conductive layer SCL2 provided between the second interlayerinsulating layer IL2 and the first sub-conductive layer SCL1.

The first sub-conductive layer SCL1 may include a metallic materialhaving excellent conductivity, flexibility and malleability. Forexample, the first sub-conductive layer SCL1 may include at least one ofgold (Au), silver (Ag), copper (Cu), aluminum (Al) and an alloy thereof.

The second sub-conductive layer SCL2 may include a material whichprevents diffusion of the materials included in the first sub-conductivelayer SCL1 and oxidation of the first sub-conductive layer SCL1. Forexample, the second sub-conductive layer SCL2 may include titanium (Ti).

The 1A-th conductive layer CL1A may further include a thirdsub-conductive layer SCL3 provided on the first sub-conductive layerSCL1. The third sub-conductive layer SCL3 may prevent oxidation of thefirst sub-conductive layer SCL1. The third sub-conductive layer SCL3 mayinclude the same material as the second sub-conductive layer SCL2, forexample, titanium (Ti).

In the first conductive patterns, the 2A-th conductive layer CL2A maycorrespond to an additional conductive layer provided between the secondinterlayer insulating layer IL2 and the 1A-th conductive layer CL1A andinclude a material which does not form an oxide or a composite materialby reaction with an organic insulating material. For example, the 2A-thconductive layer CL2A may include a metal nitride. The metal nitride maybe a nitride of the material included in the second sub-conductive layerSCL2. For example, the 2A-th conductive layer CL2A may include titaniumnitride (TiNx). Therefore, when the second interlayer insulating layerIL2 includes an organic insulating material, the 2A-th conductive layerCL2A may prevent the organic insulating material from being diffusedinto the 1A-th conductive layer CL1A and reacting with the materialincluded in the 1A-th conductive layer CL1A.

When the second interlayer insulating layer IL2 includes an organicinsulating material and the 2A-th conductive layer CL2A is omitted, the1A-th conductive layer CL1A may be directly provided on the secondinterlayer insulating layer IL2, and the 1A-th conductive layer CL1A,particularly the second sub-conductive layer SCL2 may contact the secondinterlayer insulating layer IL2. When the second sub-conductive layerSCL2 contacts the second interlayer insulating layer IL2, the materialincluded in the second sub-conductive layer SCL2 may react with theorganic insulating material of the second interlayer insulating layerIL2 to form an oxide of the material included in the secondsub-conductive layer SCL2. Alternatively, a composite material includingthe material contained in the second sub-conductive layer SCL2 and thematerial contained in the organic insulating material may be generated.

When the 2A-th conductive layer CL2A fails to prevent diffusion of thematerials included in the second interlayer insulating layer IL2 and the1A-th conductive layer CL1A, the materials contained in the 1A-thconductive layer CL1A and the second interlayer insulating layer IL2 mayreact with each other to form the oxide or the composite material at theinterface between the second interlayer insulating layer IL2 and the2A-th conductive layer CL2A or the interface between the 1A-thconductive layer CL1A and the 2A-th conductive layer CL2A. In addition,when the 2A-th conductive layer CL2A includes a material which reactswith the organic insulating material, the materials included in the2A-th conductive layer CL2A and the organic insulating layer may reactwith each other to form the oxide or the composite material during adeposition process of the 2A-th conductive layer CL2A.

The data line Dj of the first conductive patterns may be connected tothe second source electrode SE2 of the second transistor T2. The firstbridge pattern BRP1 of the first conductive patterns may be connected tothe seventh source electrode SE7 of the seventh transistor T7. Inaddition, the connection line CNL of the first conductive patterns maybe connected to the third drain electrode DE3 of the third transistorT3. Each of the third drain electrode DE3 and the seventh sourceelectrode SE7 may include a semiconductor material.

Portions of the data line Dj, the first bridge pattern BRP1 and theconnection line CNL which are connected to the second source electrodeSE2, the third drain electrode DE3 and the seventh source electrode SE7may be the 2A-th conductive layer CL2A. The 2A-th conductive layer CL2Amay contain 9 atomic percent (at %) to 45 at % of nitrogen so that the2A-th conductive layer CL2A may be connected to the second sourceelectrode SE2, the third drain electrode DE3 or the seventh sourceelectrode SE7 and maintain conductivity.

In addition, the 2A-th conductive layer CL2A may have a smallerthickness than the first sub-conductive layer SCL1, the secondsub-conductive layer SCL2 and the third sub-conductive layer SCL3. Forexample, the 2A-th conductive layer CL2A may have a thickness rangingfrom 10 Å to 100 Å.

The first conductive patterns may be covered by the third interlayerinsulating layer IL3. The power supply line PL and the second bridgepattern BRP2 may be provided on the third interlayer insulating layerIL3. The second bridge pattern BRP2 may be connected to the first bridgepattern BRP1. The power supply line PL and the second bridge patternBRP2 may be one of the second conductive patterns provided on the thirdinterlayer insulating layer IL3.

The third interlayer insulating layer IL3 may include the firstinsulating layer IL31 including an inorganic insulating material and thesecond insulating layer IL32 provided on the first insulating layer IL31and including an organic insulating material. The organic insulatingmaterial may be at least one of polyacrylates resin, epoxy resin,phenolic resin, polyamides resin, polyimides resin, unsaturatedpolyesters resin, poly-phenylene ethers resin, poly-phenylene sulfidesresin, and benzocyclobutenes resin. Each of the above-described organicinsulating materials may include carbon and oxygen. In addition, theorganic insulating material may further include at least one of oxygen,nitrogen, fluorine and sulfur.

The second conductive patterns may be provided on the second insulatinglayer IL32 of the third interlayer insulating layer IL3. The secondconductive patterns may have a similar structure to the first conductivepatterns. For example, the second conductive patterns may include a1B-th conductive layer CL1B provided on the second insulating layer IL32and a 2B-th conductive layer CL2B provided between the third insulatinglayer IL3 and the 1B-th conductive layer CL1B.

The 1B-th conductive layer CL1B may include the first sub-conductivelayer SCL1 provided on the 2B-th conductive layer CL2B and the secondsub-conductive layer SCL2 provided between the 2B-th conductive layerCL2B and the first sub-conductive layer SCL1. In addition, the 1B-thconductive layer CL1B may further include the third sub-conductive layerSCL3 provided on the first sub-conductive layer SCL1.

In the second conductive patterns, the 2B-th conductive layer CL2B maybe an additional conductive layer provided between the third interlayerinsulating layer IL3 and the 1B-th conductive layer CL1B. Like the 2A-thconductive layer CL2A, the 2B-th conductive layer CL2B may include amaterial which does not produce an oxide or a composite material byreaction with the organic insulating material. For example, the 2B-thconductive layer CL2B may include a metal nitride. The metal nitride maybe a nitride of the material included in the second sub-conductive layerSCL2. For example, the 2B-th conductive layer CL2B may include titaniumnitride (TiNx). Therefore, the 2B-th conductive layer CL2B may preventthe organic insulating material included in the second insulating layerIL32 from being diffused into the 1B-th conductive layer CL1B andreacting with the material included in the 1B-th conductive layer CL1B.

When the 2B-th conductive layer CL2B is omitted, the 1B-th conductivelayer CL1B may be directly provided on the second insulating layer IL32,and the 1B-th conductive layer CL1B, particularly, the secondsub-conductive layer SCL2 may contact the second insulating layer IL32.When the second sub-conductive layer SCL2 contacts the second insulatinglayer IL32, the material included in the second sub-conductive layerSCL2 may react with the material included in the second insulating layerIL32 to produce an oxide of the material included in the secondsub-conductive layer SCL2. Alternatively, a composite material includingthe material included in the second sub-conductive layer SCL2 and amaterial contained in the organic insulating material may be generated.

When the 2B-th conductive layer CL2B fails to prevent diffusion of thematerials included in the second insulating layer IL32 and the 1B-thconductive layer CL1B, the materials included in the 1B-th conductivelayer CL1B and the second insulating layer IL32 may react with eachother to form the oxide or the composite material at the interfacebetween the second insulating layer IL32 and the 2B-th conductive layerCL2B or the interface between the 1B-th conductive layer CL1B and the2B-th conductive layer CL2B. In addition, when the 2B-th conductivelayer CL2B includes a material reacting with the organic insulatingmaterial, the materials included in the 2B-th conductive layer CL2B andthe organic insulating layer may react with each other to form the oxideor the composite material during a deposition process of the 2B-thconductive layer CL2B.

The 2B-th conductive layer CL2B of the second bridge pattern BRP2, amongthe second conductive patterns, may be connected to the first bridgepattern BRP1. The 2B-th conductive layer CL2B of the second bridgepattern BRP2 may contain 9 at % to 55 at % of nitrogen so that the 2B-thconductive layer CL2B of the second bridge pattern BRP2 may be connectedto the first bridge pattern BRP1 and maintain conductivity.

In addition, the 2B-th conductive layer CL2B may have a smallerthickness than the first sub-conductive layer SCL1, the secondsub-conductive layer SCL2 and the third sub-conductive layer SCL3. Forexample, the 2B-th conductive layer CL2B may have a thickness rangingfrom 10 Å to 100 Å.

As illustrated in FIGS. 9, 10, 13 and 14, the oxide or the compositematerial may be present in the form of a residual layer at the interfacebetween the 1A-th conductive layer CL1A and the organic insulatinglayer, the second interlayer insulating layer IL2, and the interfacebetween the 1B-th conductive layer CL1B and the organic insulatinglayer, the third interlayer insulating layer IL3. The residual layerincluding the oxide or the composite material may not be removed duringan etch process for forming the first conductive patterns or the secondconductive patterns. During the process of forming the first conductivepatterns or the second conductive patterns, the residual layer may notbe removed by an etching gas or an etchant for removing the firstconductive layer or the second conductive layer. In other words, anadditional process for removing the residual layer may be required toremover the residual layer.

However, according to an embodiment, when a metal nitride, the 2A-thconductive layer CL2A and the 2B-th conductive layer CL2B exists betweenthe 1A-th conductive layer CL1A and the second interlayer insulatinglayer IL2, and between the 1B-th conductive layer CL1B and the thirdinterlayer insulating layer IL3, the metal nitride may preventinter-diffusion of atoms in the 1A-th conductive layer CL1A and thesecond interlayer insulating layer IL2, and in the 1B-th conductivelayer CL1B and the third interlayer insulating layer IL3 to form anoxide or a composite material. Therefore, as illustrated in FIGS. 1, 12,15 and 16, the formation of the residual layer including the oxide orthe composite material at the interface between 1A-th conductive layerCL1A and the second interlayer insulating layer IL2, and between the1B-th conductive layer CL1B and the third interlayer insulating layerIL3 may be prevented.

A method of manufacturing the first conductive patterns and the secondconductive patterns is described below. Hereinafter, for convenience ofexplanation, a method of manufacturing the second conductive patterns isdescribed as an example.

First, the second insulating layer IL32 of the third interlayerinsulating layer IL3 including the organic insulating material may beformed. The second insulating layer IL32 may be formed by spin coating.

After the second insulating layer IL32 is formed, the 2B-th conductivelayer CL2B may be formed on the second insulating layer IL2.

The 2B-th conductive layer CL2B, a diffusion barrier, may include amaterial which does not react with an organic insulating material andprevents an inter-diffusion of atoms in the second insulating layer IL32and in the 1B-th conductive layer CL1B. For example, the 2B-thconductive layer CUB may include titanium nitride (TiNx).

The 2B-th conductive layer CL2B may be formed by one of chemical vapordeposition (CVD), atomic layer deposition (ALD) and reactive sputteringdeposition. The reactive sputtering deposition may be performed to formtitanium nitride (TiNx) using a target including titanium (Ti) and areaction gas including nitrogen (N2).

After the 2B-th conductive layer CL2B is formed, the 1B-th conductivelayer CL1B may be formed on the 2B-th conductive layer CL2B. The 1B-thconductive layer CL1B may include the second sub-conductive layer SCL2,the first sub-conductive layer SCL1 and the third sub-conductive layerSCL3 that are sequentially stacked. The first sub-conductive layer SCL1,the second sub-conductive layer SCL2 and the third sub-conductive layerSCL3 may be formed by a physical deposition method such as sputtering.

The first sub-conductive layer SCL1 may include at least one of gold(Au), silver (Ag), copper (Cu), aluminum (Al) and an alloy thereof. Thesecond sub-conductive layer SCL2 and the third sub-conductive layer SCL3may include titanium (Ti).

After the 1B-th conductive layer CL1B is formed, the 1B-th conductivelayer CL1B and the 2B-th conductive layer CL2B may be etched byphotolithography. The second conductive patterns may be formed byetching the 1B-th conductive layer CL1B and the 2B-th conductive layerCL2B. The 1B-th conductive layer CL1B and the 2B-th conductive layerCL2B may be formed at the same time using the same dry etching process.

The first conductive patterns may be formed by the same manufacturingprocesses as the second conductive patterns, except that the firstconductive patterns are formed on the second interlayer insulating layerIL2.

FIG. 17 is a cross-sectional diagram taken along the line I-I′ of FIG. 2for illustrating a display area and a non-display area of a displaydevice. FIG. 18 is an enlarged view of the area EA3 of FIG. 17. Forconvenience of explanation, as illustrated in FIG. 17, one transistorand one display element may be provided on one pixel.

Referring to FIGS. 1 to 8, 17, and 18, the display device may includethe display area DA and the non-display area NDA.

Hereinafter, the display area DA is described first, and the non-displayarea NDA is then described.

First, in the display area DA, the plurality of pixels PXL may beprovided on the substrate SUB. Each of the plurality of pixels PXL mayinclude at least one transistor, the display element OLED connected tothe transistor, and the first bridge pattern BRP1 and the second bridgepattern BRP2 connecting the transistor and the display element OLED toeach other.

The transistor may be the seventh transistor T7 shown in FIGS. 4 to 6.The transistor may include an active pattern ACT, a gate electrode GE, asource electrode SE and a drain electrode DE.

According to an embodiment, the source electrode SE and the drainelectrode DE may extend from both sides of the active pattern ACT. Eachof the active pattern ACT, the source electrode SE and the drainelectrode DE may include a semiconductor layer doped or undoped withimpurities. For example, each of the source electrode SE and the drainelectrode DE may include a semiconductor layer doped with impurities andthe active pattern ACT may include a semiconductor layer undoped withimpurities.

The gate insulating layer GI may be provided between the gate electrodeGE and the active pattern ACT, the source electrode SE and the drainelectrode DE. The gate insulating layer GI may include at least one ofan organic insulating layer and an inorganic insulating layer.

The gate electrode GE may be provided on the gate insulating layer GI.The gate electrode GE may be formed to cover the active pattern ACT.

The buffer layer BUL may be provided between the substrate SUB and thetransistor. The buffer layer BUL may include at least one of an organicinsulating material and an inorganic insulating material.

The transistor may be covered by the first interlayer insulating layerIL1 and the second interlayer insulating layer IL2 that are sequentiallystacked.

The first interlayer insulating layer IL1 may include at least one ofpolysiloxane, silicon oxide, silicon nitride and silicon oxynitride.

The second interlayer insulating layer IL2 may include at least one ofan inorganic insulating layer and an organic insulating layer. Forexample, the second interlayer insulating layer IL2 may include at leastone inorganic insulating layer. The inorganic insulating layer mayinclude at least one of silicon oxide, silicon nitride and siliconoxynitride. In addition, the second interlayer insulating layer IL2 mayinclude at least one organic insulating layer. The organic insulatinglayer may include at least one of photoresist, polyacrylates resin,epoxy resin, phenolic resin, polyamides resin, polyimides resin,unsaturated polyesters resin, poly-phenylene ethers resin,poly-phenylene sulfides resin, and benzocyclobutenes resin. In addition,the second interlayer insulating layer IL2 may have a multilayerstructure including at least one inorganic insulating layer and at leastone organic insulating layer.

The first bridge pattern BRP1 connected to the source electrode SE ofthe transistor may be provided on the second interlayer insulating layerIL2. The first bridge pattern BRP1 may be covered by the thirdinterlayer insulating layer IL3. The third interlayer insulating layerIL3 may include the first insulating layer IL31 and the secondinsulating layer IL32 provided on first insulating layer IL31. The firstinsulating layer IL31 may include an inorganic insulating material. Thesecond insulating layer IL32 may include an organic insulating material.

The second bridge pattern BRP2 connected to the first bridge patternBRP1 may be provided on the third interlayer insulating layer IL3. Thesecond bridge pattern BRP2 may be covered by the fourth interlayerinsulating layer IL4. The fourth interlayer insulating layer IL4 mayinclude the same organic insulating material as the third interlayerinsulating layer L3.

The display element OLED connected to the second bridge pattern BRP2 maybe provided on the fourth interlayer insulating layer IL4. The displayelement OLED may include the first electrode AD provided on the fourthinterlayer insulating layer IL4, the second electrode CD provided on thefirst electrode AD to overlap the first electrode AD, and the emittinglayer EML disposed between the first electrode AD and the secondelectrode CD.

The sealing layer SLM may be provided on the second electrode CD. Thesealing layer SLM may prevent intrusion of oxygen and moisture into thedisplay element OLED. The sealing layer SLM may include a plurality ofinorganic layers (not illustrated) and a plurality of organic layers(not illustrated).

Subsequently, the non-display area NDA is described below. Hereinafter,the non-display area NDA will be briefly described to avoid redundantdescription, or a detailed description thereof will be omitted.

The wiring lines LP may be provided on the non-display area NDA. Thebent area BA may be provided at a portion of the non-display area NDA,so that the substrate SUB may be folded or bent.

The wiring lines LP may connect the driver and the pixels PXL. Thewiring lines LP may include a first wiring line L1 and a second wiringline L2.

Each of the first wiring line L1 and the second wiring line L2 may beone of the scan lines Si−1 and Si, the data line Dj, the initializationline IPL and the power supply line PL. According to an embodiment, thefirst wiring line L1 may be the data line Dj and the second wiring lineL2 may be the power supply line PL.

The first wiring line L1 may include a plurality of sub-wiring lines.For example, the first wiring line L1 may include first, second andthird sub-wiring lines L11, L12 and L13. Each of the first sub-wiringlines L11 may be connected to each of the second sub-wiring lines L12.Each of the second sub-wiring lines L12 may be connected to each of thethird sub-wiring lines L13. For convenience of explanation, in FIG. 17,some of the first to third sub-wiring lines L11 to L13 are schematicallyillustrated. The first sub-wiring line L11 may be connected to thedriver, and the third sub-wiring line L13 may be connected to the pixelPXL.

In addition, the first sub-wiring lines L11 and the third sub-wiringlines L13 may be provided on the gate insulating layer GI. The firstsub-wiring lines L11 may be provided on the first flat area FA1 and thethird sub-wiring lines L13 may be provided on the second flat area FA2.The first sub-wiring lines L11 and the third sub-wiring lines L13 may beformed using the same material as the gate electrode GE by the sameprocess performed to form the gate electrode GE.

In the non-display area NDA, the buffer layer BUL, the gate insulatinglayer GI, the first interlayer insulating layer IL1, and the secondinterlayer insulating layer IL2 may be sequentially stacked on thesubstrate SUB. The buffer layer BUL, the gate insulating layer GI, thefirst interlayer insulating layer IL1, and the second interlayerinsulating layer IL2 may have an opening OPN in the bent area BA. Theopening OPN may be formed by removing the buffer layer BUL, the gateinsulating layer GI, the first interlayer insulating layer IL1, and thesecond interlayer insulating layer IL2 on the bent area BA. According toan embodiment, portions of the buffer layer BUL, the gate insulatinglayer GI, the first interlayer insulating layer IL1, and the secondinterlayer insulating layer IL2 which correspond to the bent area BA maynot be removed.

When the opening OPN corresponds to the bent area BA, it may mean thatthe opening OPN may overlap with the bent area BA. The opening OPN mayhave a greater width than the bent area BA. According to an embodiment,for convenience of explanation, the opening OPN may have the same widthas the bent area BA as illustrated in FIG. 17. However, the width of theopening OPN may have a greater width than the bent area BA.

As illustrated in 17, inner side surfaces of the buffer layer BUL, thegate insulating layer GI, the first interlayer insulating layer IL1, andthe second interlayer insulating layer IL2 may coincide with each otherand be arranged in a straight line. However, the inventive concept isnot limited thereto. For example, the portion removed from the bufferlayer BUL may have a smaller area than the portion removed from thesecond interlayer insulating layer IL2. According to an embodiment, theportion removed from the buffer layer BUL may be defined as having asmaller area than those of the gate insulating layer GI, the firstinterlayer insulating layer IL1, and the second interlayer insulatinglayer IL2.

A bent insulating layer ILB may be provided in the opening OPN. The bentinsulating layer ILB may fill at least a portion of the opening OPN.According to an embodiment, the bent insulating layer ILB may completelyfill the opening OPN. In addition, according to an embodiment, the bentinsulating layer ILB may fill the opening OPN and at the same time coveran area adjacent to the opening OPN, for example, a portion of the upperpart of the second interlayer insulating layer IL2 corresponding to thefirst and/or second flat areas FA1 and/or FA2.

The bent insulating layer ILB may be an organic insulating layerincluding an organic material. For example, the bent insulating layerILB may include at least one of photoresist, polyacrylates resin, epoxyresin, phenolic resin, polyamides resin, polyimides resin, unsaturatedpolyesters resin, poly-phenylene ethers resin, poly-phenylene sulfidesresin, and benzocyclobutenes resin.

When the second interlayer insulating layer IL2 includes the organicinsulating material, the bent insulating layer ILB may be omitted. Morespecifically, the opening OPN may be formed by removing portions of thebuffer layer BUL, the gate insulating layer GI and the first interlayerinsulating layer IL1 corresponding to the bent area BA. The opening OPNmay be filled with the second interlayer insulating layer IL2.Therefore, the second interlayer insulating layer IL2 may replace thebent insulating layer ILB in the opening OPN.

The second sub-wiring line L12 may be provided on the second interlayerinsulating layer IL2 and the bent insulating layer ILB. The secondsub-wiring line L12 may extend from the first flat area FA1 via the bentarea BA to the second flat area FA2 and be provided on the bentinsulating layer ILB. The second sub-wiring line L12 may be provided onthe second interlayer insulating layer IL2 at a position where the bentinsulating layer ILB is not provided.

The second sub-wiring line L12 may be formed using the same material asthe first bridge pattern BRP1 by the same process performed to form thefirst bridge pattern BRP1. In other words, the second sub-wiring lineL12 may be one of the first conductive patterns. Therefore, the secondsub-wiring line L12 may include the 1A-th conductive layer CL1A providedon the bent insulating layer ILB and the 2A-th conductive layer CL2Aprovided between the bent insulating layer ILB and the 1A-th conductivelayer CL1A.

As illustrated in FIG. 17, the display device may not be bent. However,the display device may be bent at the bent area BA. After a displaydevice according to an embodiment may be manufactured to be flat, thedisplay device may then be bent.

According to an embodiment, for convenience of explanation, the bentarea BA is illustrated as coinciding with the portions removed from thebuffer layer BUL, the gate insulating layer GI and the first interlayerinsulating layer IL1 including the inorganic insulating material.However, the bent area BA may not coincide with the portions removedfrom the buffer layer BUL, the gate insulating layer GI and the firstinterlayer insulating layer IL1. For example, although the bent area BAgenerally corresponds to the portions removed from the buffer layer BUL,the gate insulating layer GI and the first interlayer insulating layerIL1, the bent area BA may be partially wider or narrower than theportions removed from the buffer layer BUL, the gate insulating layer GIand the first interlayer insulating layer IL1 if necessary. In addition,according to an embodiment, it is illustrated that the bent area BA islocated only in the non-display area NDA. However, the inventive conceptis not limited thereto. For example, the bent area BA may be providedacross the non-display area NDA and the display area DA, or in thedisplay area DA.

The third interlayer insulating layer IL3 may be provided on thesubstrate SUB where the second sub-wiring line L12 is formed. The thirdinterlayer insulating layer IL3 may include the first insulating layerIL31 including an inorganic insulating material and the secondinsulating layer IL32 provided on the first insulating layer IL1 andincluding an organic insulating material. Since the first insulatinglayer IL31 includes the inorganic insulating material, the firstinsulating layer IL31 may not be provided at positions corresponding tothe bent area BA, such as the buffer layer BUL, the gate insulatinglayer GI and the first interlayer insulating layer IL1.

The second wiring line L2 may be provided on the second insulating layerIL32 of the third interlayer insulating layer IL3. The second wiringline L2 may be formed using the same material as the second bridgepattern BRP2 by the same process as the second bridge pattern BRP2. Inother words, the second wiring line L2 may be one of the secondconductive patterns. Therefore, the second wiring line L2 may includethe 1B-th conductive layer CL1B provided on the second insulating layerIL32 and the 2B-th conductive layer CL2B provided between the secondinsulating layer IL32 and the 1B-th conductive layer CL1B.

The 1A-th conductive layer CL1A and the 1B-th conductive layer CL1B mayinclude the first sub-conductive layer SCL1 provided on the 2A-thconductive layer CL2A and the 2B-th conductive layer CL2B, and thesecond sub-conductive layer SCL2 provided between the 2A-th conductivelayer CL2A and the first sub-conductive layer SCL1 or between the 2B-thconductive layer CL2B and the first sub-conductive layer SCL1.

The first sub-conductive layer SCL1 may include a metallic materialhaving excellent conductivity, flexibility and malleability. Forexample, the first sub-conductive layer SCL1 may include at least one ofgold (Au), silver (Ag), copper (Cu), aluminum (Al) and an alloy thereof.

The second sub-conductive layer SCL2 may include a material whichprevents diffusion of the materials included in the first sub-conductivelayer SCL1 and oxidation of the first sub-conductive layer SCL1. Forexample, the second sub-conductive layer SCL2 may include titanium (Ti).

The 1A-th conductive layer CL1A and the 1B-th conductive layer CL1B mayinclude the third sub-conductive layer SCL3 provided on the firstsub-conductive layer SCL1. The third sub-conductive layer SCL3 mayprevent oxidation of the first sub-conductive layer SCL1. For example,the third sub-conductive layer SCL3 may include titanium (Ti).

The 2A-th conductive layer CL2A may prevent the material included in thebent insulating layer ILB from being diffused into the 1A-th conductivelayer CL1A and the material included in the 2A-th conductive layer CL2Afrom being diffused into the bent insulating layer ILB. The 2B-thconductive layer CL2B may prevent the material included in the secondinsulating layer IL32 from being diffused into the 1B-th conductivelayer CL1BA and the material included in the 1B-th conductive layer CL1Bfrom being diffused into the second insulating layer IL32. In addition,the 2A-th conductive layer CL2A and the 2B-th conductive layer CL2B mayinclude a material which does not produce an oxide or a compositematerial by reaction with the organic insulating material. For example,the 2A-th conductive layer CL2A and the 2B-th conductive layer CL2B mayinclude a metal nitride. The metal nitride may be a nitride of thematerial included in the second sub-conductive layer SCL2. For example,the 2A-th conductive layer CL2A and the 2B-th conductive layer CL2B mayinclude titanium nitride (TiNx).

The fourth interlayer insulating layer IL4 may be provided on the secondwiring line L2. An insulating layer including the same material as thepixel defining layer PDL may be provided on the fourth interlayerinsulating layer IL4.

FIGS. 19 to 23 are cross-sectional diagrams illustrating conductivepatterns of a display device according to an embodiment.

Referring to FIGS. 1 to 8 and 17 to 23, at least some of the conductivepatterns CP applied to the display device may be provided on a lowerinsulating layer LIL and covered by an upper insulating layer UIL.

The lower insulating layer LIL and the upper insulating layer UIL mayinclude an organic insulating material. For example, each of the lowerinsulating layer LIL and the upper insulating layer UIL may include atleast one of photoresist, polyacrylates resin, epoxy resin, phenolicresin, polyamides resin, polyimides resin, unsaturated polyesters resin,poly-phenylene ethers resin, poly-phenylene sulfides resin, andbenzocyclobutenes resin.

In addition, the lower insulating layer LIL may include an inorganicinsulating material. For example, the lower insulating layer LIL mayinclude at least one of silicon oxide, silicon nitride and siliconoxynitride.

The lower insulating layer LIL according to an embodiment may be one ofthe second interlayer insulating layer IL2, the third interlayerinsulating layer IL3 and the bent insulating layer ILB as shown in FIGS.5, 6 and 17. According to an embodiment, the upper insulating layer UILmay be one of the third interlayer insulating layer IL3 and the fourthinterlayer insulating layer IL4 as shown in FIGS. 5, 6 and 17.

The conductive patterns CP may have various stacked structures. Forexample, as illustrated in FIGS. 18 and 19, the conductive patterns CPmay include the first conductive layer CL1 provided on the lowerinsulating layer LIL and the second conductive layer CL2 providedbetween the lower insulating layer LIL and the first conductive layerCL1.

In addition, as illustrated in FIGS. 20 and 22, the conductive patternsCP may include the first conductive layer CL1 provided on the lowerinsulating layer LIL, the second conductive layer CL2 provided betweenthe lower insulating layer LIL and the first conductive layer CL1, and athird conductive layer CL3 provided on the first conductive layer CL1.

In addition, as illustrated in FIG. 23, the conductive patterns CP mayinclude the first conductive layer CL1 provided on the lower insulatinglayer LIL and the third conductive layer CL3 provided on the firstconductive layer CL1.

The first conductive layer CL1 may have various stacked structures. Forexample, as illustrated in FIGS. 18, 20 and 23, the first conductivelayer CL1 may include the first sub-conductive layer SCL1, the secondsub-conductive layer SCL2 provided on the first sub-conductive layerSCL1, and the third sub-conductive layer SCL3 provided on the firstsub-conductive layer SCL1.

In addition, as illustrated in FIGS. 19 and 21, the first conductivelayer CL1 may include the first sub-conductive layer SCL1 provided onthe second conductive layer CL2 and the third sub-conductive layer SCL3provided on the first sub-conductive layer SCL1.

In addition, as illustrated in FIG. 22, the first conductive layer CL1may include a single conductive layer provided on the second conductivelayer CL2. The first conductive layer CL1 may be the firstsub-conductive layer SCL1.

The first sub-conductive layer SCL1 may include a metallic materialhaving excellent conductivity, flexibility and malleability. Forexample, the first sub-conductive layer SCL1 may include at least one ofgold (Au), silver (Ag), copper (Cu), aluminum (Al) and an alloy thereof.

The second sub-conductive layer SCL2 may include a material whichprevents diffusion of the materials included in the first sub-conductivelayer SCL1 and oxidation of the first sub-conductive layer SCL1. Forexample, the second sub-conductive layer SCL2 may include titanium (Ti).

The 1A-th conductive layer CL1A may further include the thirdsub-conductive layer SCL3 provided on the first sub-conductive layerSCL1. The third sub-conductive layer SCL3 may prevent oxidation of thefirst sub-conductive layer SCL1 and include the same material as thesecond sub-conductive layer SCL2. For example, the third sub-conductivelayer SCL3 may include titanium (Ti).

The second conductive layer CL2 may prevent the material included in thelower insulating layer LIL from being diffused into the first conductivelayer CL1 and the material included in the first conductive layer CL1from being diffused into the third interlayer insulating layer IL3. Inaddition, the second conductive layer CL2 may include a material whichdoes not form an oxide or a composite material by reaction with theorganic insulating material of the lower insulating layer LIL. Forexample, the second conductive layer CL2 may include a metal nitride.The metal nitride may be a nitride of the material included in thesecond sub-conductive layer SCL2. For example, the second conductivelayer CL2 may include titanium nitride (TiNx).

The third conductive layer CL3 may include the same material as thesecond conductive layer CL2. For example, the third conductive layer CL3may include a metal nitride. The third conductive layer CL3 may beprovided to connect two different conductive patterns CP, such as thefirst bridge pattern BRP1 and the second bridge pattern BRP2 asillustrated in FIGS. 5, 6, and 17. The third conductive layer CL3 may beincluded in the lower conductive pattern CP between the two conductivepatterns CP, for example, the first bridge pattern BRP1.

According to an embodiment, a conductive pattern arranged on an organiclayer may be prevented from reacting with the organic layer to generatean oxide or a composite material. Therefore, an increase in number ofetch processes performed to form the conductive pattern caused by theoxide or the composite material may be avoided. Accordingly,manufacturing time of a display device having the conductive pattern maybe reduced.

Although exemplary embodiments are disclosed herein, these embodimentsshould not be construed to limit a scope of the inventive concept. Thoseof ordinary skill in the art would recognize that various changes inform and details may be made without departing from the spirit andscope.

What is claimed is:
 1. A conductive pattern, comprising: an insulatinglayer including organic material; a first conductive layer provided onthe insulating layer and including at least a first sub-conductivelayer; and an additional conductive layer provided between theinsulating layer and the first conductive layer, or on the firstconductive layer, wherein the additional conductive layer includes ametal nitride.
 2. The conductive pattern of claim 1, wherein theadditional conductive layer is a second conductive layer providedbetween the insulating layer and the first conductive layer.
 3. Theconductive pattern of claim 2, wherein the first conductive layerfurther comprises a second sub-conductive layer provided between thesecond conductive layer and the first sub-conductive layer, and thesecond conductive layer includes a nitride of a material included in thesecond sub-conductive layer.
 4. The conductive pattern of claim 3,wherein the second sub-conductive layer includes titanium (Ti).
 5. Theconductive pattern of claim 4, wherein the second conductive layerincludes a titanium nitride.
 6. The conductive pattern of claim 3,further comprising a third sub-conductive layer provided on the firstsub-conductive layer, wherein the third sub-conductive layer includesthe same material as the second sub-conductive layer.
 7. The conductivepattern of claim 6, wherein the third sub-conductive layer includestitanium (Ti).
 8. The conductive pattern of claim 3, further comprisinga third conductive layer provided on the first sub-conductive layer,wherein the third conductive layer includes the same material as thesecond conductive layer.
 9. The conductive pattern of claim 8, whereinthe second conductive layer includes a titanium nitride.
 10. Theconductive pattern of claim 2, further comprising a third sub-conductivelayer provided on the first sub-conductive layer, wherein the secondconductive layer includes a nitride of a material included in the thirdsub-conductive layer.
 11. The conductive pattern of claim 10, furthercomprising a third conductive layer provided on the third sub-conductivelayer, wherein the third conductive layer includes the same material asthe second conductive layer.
 12. The conductive pattern of claim 2,further comprising a third conductive layer provided on the firstsub-conductive layer, wherein the third conductive layer includes ametal nitride.
 13. The conductive pattern of claim 12, wherein thesecond conductive layer and the third conductive layer include atitanium nitride.
 14. The conductive pattern of claim 2, wherein thefirst sub-conductive layer includes at least one of gold (Au), silver(Ag), copper (Cu), aluminum (Al) and an alloy thereof.
 15. Theconductive pattern of claim 1, wherein the additional conductive layeris a third conductive layer provided on the first conductive layer, andthe third conductive layer includes a metal nitride.
 16. A displaydevice, comprising: a substrate including a display area and anon-display area; at least one transistor provided in the display areaof the substrate; a first insulating layer covering the transistor; afirst bridge pattern provided on the first insulating layer andconnected to the transistor; a second insulating layer covering thefirst bridge pattern and including an organic insulating material; asecond bridge pattern provided on the second insulating layer andconnected to the first bridge pattern; and a display element connectedto the second bridge pattern, wherein the second bridge patterncomprises: a first conductive layer including at least a firstsub-conductive layer; and a second conductive layer provided between thesecond insulating layer and the first conductive layer, wherein thesecond conductive layer includes a metal nitride.
 17. The display deviceof claim 16, wherein the first conductive layer further comprises asecond sub-conductive layer provided between the second conductive layerand the first sub-conductive layer, and the second conductive layerincludes a nitride of a material included in the second sub-conductivelayer.
 18. The display device of claim 17, wherein the secondsub-conductive layer includes titanium (Ti), and the second conductivelayer includes a titanium nitride.
 19. The display device of claim 17,further comprising a third sub-conductive layer provided on the firstsub-conductive layer, wherein the third sub-conductive layer includesthe same material as the second sub-conductive layer.
 20. The displaydevice of claim 19, wherein the third sub-conductive layer includestitanium (Ti), and the second conductive layer includes a titaniumnitride.
 21. The display device of claim 19, wherein the transistorincludes an active pattern, a gate electrode, a source electrode and adrain electrode provided on the substrate, the source electrode and thedrain electrode extending from both sides of the active pattern, andeach of the source electrode and the drain electrode includes asemiconductor layer doped with impurities, and the active patternincludes a semiconductor layer undoped with impurities.
 22. The displaydevice of claim 21, wherein the first insulating layer includes anorganic insulating material, wherein the first bridge pattern comprises:a first conductive layer provided on the first insulating layer andincluding at least a first sub-conductive layer; and a second conductivelayer provided between the first insulating layer and the firstconductive layer, wherein the second conductive layer includes a metalnitride.
 23. The display device of claim 22, wherein in the first bridgepattern, the first conductive layer further comprises a secondsub-conductive layer provided between the second conductive layer andthe first sub-conductive layer, and the second conductive layer includesa nitride of a material included in the second sub-conductive layer. 24.The display device of claim 23, wherein in the first bridge pattern, thesecond sub-conductive layer includes titanium (Ti) and the secondconductive layer includes a titanium nitride.
 25. The display device ofclaim 23, further comprising a third sub-conductive layer provided onthe first sub-conductive layer in the first bridge pattern, wherein thethird sub-conductive layer includes the same material as the secondsub-conductive layer.
 26. The display device of claim 25, wherein in thefirst bridge pattern, the third sub-conductive layer includes titanium(Ti), and the second conductive layer includes a titanium nitride. 27.The display device of claim 22, further comprising a thirdsub-conductive layer provided on the first sub-conductive layer in thefirst bridge pattern, wherein the second conductive layer includes anitride of a material included in the third sub-conductive layer. 28.The display device of claim 22, further comprising a third conductivelayer provided on the first sub-conductive layer in the first bridgepattern, wherein the third conductive layer includes the same materialas the second conductive layer.
 29. The display device of claim 16,further comprising a third sub-conductive layer provided on the firstsub-conductive layer, wherein the second conductive layer includes anitride of a material included in the third sub-conductive layer.
 30. Adisplay device, comprising: a substrate including a display area and anon-display area; at least one transistor provided in the display areaof the substrate; a display element connected to the transistor, and aconductive pattern connected to the transistor or the display elementand provided on an organic layer, wherein the conductive patterncomprises: a first conductive layer including at least a firstsub-conductive layer; and a second conductive layer provided between theorganic layer and the first conductive layer, wherein the secondconductive layer includes a metal nitride.
 31. The display device ofclaim 30, wherein the first conductive layer further comprises a secondsub-conductive layer provided between the second conductive layer andthe first sub-conductive layer, and the second conductive layer includesa nitride of a material included in the second sub-conductive layer. 32.The display device of claim 31, wherein the second sub-conductive layerincludes titanium (Ti), and the second conductive layer includes atitanium nitride.
 33. The display device of claim 31, further comprisinga third sub-conductive layer provided on the first sub-conductive layer,wherein the third sub-conductive layer includes the same material as thesecond sub-conductive layer.
 34. The display device of claim 33, whereinthe third sub-conductive layer includes titanium (Ti), and the secondconductive layer includes a titanium nitride.
 35. The display device ofclaim 31, further comprising a third conductive layer provided on thefirst sub-conductive layer, wherein the third conductive layer includesthe same material as the second conductive layer.
 36. The display deviceof claim 30, further comprising a third sub-conductive layer provided onthe first sub-conductive layer, wherein the second conductive layerincludes a nitride of a material included in the third sub-conductivelayer.
 37. The display device of claim 36, further comprising a thirdconductive layer provided on the third sub-conductive layer, wherein thethird conductive layer includes the same material as the secondconductive layer.
 38. The display device of claim 30, further comprisinga third conductive layer provided on the first sub-conductive layer,wherein the third conductive layer includes the same material as thesecond conductive layer.
 39. A conductive pattern, comprising: aninsulating layer including organic material; a first conductive layerprovided on the insulating layer and including at least a firstsub-conductive layer; and an additional conductive layer providedbetween the insulating layer and the first conductive layer, or on thefirst conductive layer, wherein the additional conductive layer includesa material not reacting with a material included in the insulatinglayer.
 40. The conductive pattern of claim 39, wherein the additionalconductive layer is a second conductive layer provided between theinsulating layer and the first conductive layer.
 41. The conductivepattern of claim 40, wherein the second conductive layer includes ametal nitride.
 42. The conductive pattern of claim 41, wherein the firstconductive layer further comprises a second sub-conductive layerprovided between the second conductive layer and the firstsub-conductive layer, and the second conductive layer includes a nitrideof a material included in the second sub-conductive layer.
 43. Theconductive pattern of claim 42, wherein the second sub-conductive layerincludes titanium (Ti), and the second conductive layer includes atitanium nitride.
 44. The conductive pattern of claim 42, furthercomprising a third sub-conductive layer provided on the firstsub-conductive layer, wherein the third sub-conductive layer includesthe same material as the second sub-conductive layer.
 45. The conductivepattern of claim 44, wherein the third sub-conductive layer includestitanium (Ti), and the second conductive layer includes a titaniumnitride.
 46. The conductive pattern of claim 42, further comprising athird conductive layer provided on the first sub-conductive layer,wherein the third conductive layer includes the same material as thesecond conductive layer.
 47. The conductive pattern of claim 41, furthercomprising a third sub-conductive layer provided on the firstsub-conductive layer, wherein the second conductive layer includes anitride of a material included in the third sub-conductive layer. 48.The conductive pattern of claim 47, further comprising a thirdconductive layer provided on the third sub-conductive layer, wherein thethird conductive layer includes the same material as the secondconductive layer.
 49. The conductive pattern of claim 39, wherein theadditional conductive layer is a third conductive layer provided on thefirst conductive layer, and the third conductive layer includes a metalnitride.